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Features
* * * * * * * * * * *
Full-field Image Sensor 3500 x 2300 Pixels Pixel 10 m x 10 m Photo-MOS Image Zone: 35 mm x 23 mm Additional Full-frame Operating Mode: 2627 x 2300 pixels of 10 m x 10 m (3 zones) Frame Readout Through One, Two or Four Outputs Built-in Region of Interest (ROI) Selection Data Rates Up to 4 x 25 MHz (Compatibility with 10 Frames/Seconds) High Dynamic Range (Up to 3000), at Room Temperature and at 25 MHz Frequency Very Low Dark Current (MPP Mode) Bayer Standard Color Mosaic Flexibility and Performance Make Device Suitable for Digital Photography, Graphic Arts, Medical and Industrial Applications
8M-pixel Color Image Sensor AT71200M
Description
Atmel's AT71200M is a progressive scan sensor based on charge-coupled device (CCD) technology. It can be used in a wide range of applications thanks to operating mode flexibility, very high definition and high dynamic range. The nominal photosensitive area is made up of 2300 x 3500 useful pixels and is split into four independent zones that are driven separately by four independant four-phase clocksets. Thus the sensor can be used in up to 12 main modes. The large format and high definition make the device suitable for any application requiring precision and accuracy. The Bayer standard RGB color mosaic has been specially designed for colorimetric applications and the three colors balanced for a 3800K standard illuminant. Two serial registers and four independent output amplifiers offer a high-frequency functionality of up to 10 frames per second and a 12-bit dynamic range.
Rev. 2133A-IMAGE-02/03
1
Pinout
Figure 1. AT71200M Pinout - Top View
19 18 17 16 15 14
VDD3
VS3
VGS3
S3 R3
LA8 LA5 LA6
VSS
VSS
LA1 LA2
LA4 S4 R4
VGS4
VS4
VDD4
VOS3 VDR3 VGL3
VSS
LA7 LA3
VSS
VGL4
VDR4 VOS4
VDEA
VSS TA VOS3
VSS
VSS
FCA
Register A
VOS4 VSS1 VFCA PA3 PA4
PB4 PB3
Zone A
PB1 PB2 PA2 PA1
Zone B
6 5 4 3 2 1
PD1 PD4 PD2 PD3
Zone C
PC4 PC1 PC3 PC2 TB FCB VDEB
Zone D
VFCB VSS1 VOS1 VSS VSS VGL1 R1 VGS1 S1
Register B
VSS LB2 LB3 LB7 VSS VSS LB6 LB5 VSS LB8
VOS2 VSS R2 S2
VOS1 VDR1 VDD1 VS1
VGL2 VDR2 VOS2 VGS2 VS2 VDD2
LB4 LB1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
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Table 1. AT71200M Pinout
Signal Name LB[1:8] LA[1:8] S[1:4] VGL[1:4] VGS[1:4] VOS[1:4] VDD[1:4] VS[1:4] R[1:4] VDR[1:4] PA[1:4] PB[1:4] PC[1:4] PD[1:4] TA, TB VDEA, VDEB VFCA, VFCB FCA, FCB VSS Pin Number F1, F2, G2, E1, J1, J2, H2, K1 J19, J18, H18, K19, F19, F18, G18, E19 D1, L1, D19, L19 C2, M2, C18, M18 C1, M1, C19, M19 A2, P2, A18, P18 A1, P1, A19, P19 B1, N1, B19, N19 D2, L2, D18, L18 B2, N2, B18, N18 P14, N14, N15, P15 A14, B14, B15, A15 P6, P5, N5, N6 A6, A5, B5, B6 B16, N4 A17, P3 P16, A4 A16, P4 A3, B3, B4, E2, G1, H1, K2, M3, B17, E18, G19, H19, K18, N16, N17, P17 Function B readout register clocks A readout register clocks Summing clocks of the outputs 1, 2, 3 and 4 Readout gate bias of the outputs 1, 2, 3 and 4 Output gate bias of the outputs 1, 2, 3 and 4 Output video signals 1, 2, 3 and 4 Output amplifier drain supplies of the outputs 1, 2, 3 and 4 Output amplifier source biases of the outputs 1, 2, 3 and 4 Reset clocks of the outputs 1, 2, 3 and 4 Reset bias of the outputs 1, 2, 3 and 4 A image zone clocks B image zone clocks C image zone clocks D image zone clocks Transfer gates from the image zone to the readout registers A and B respectively Shield drains Region of interest drains Region of interest clocks Substrate bias
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Block Diagram
Figure 2. AT71200M Block Diagram - Top View
LAi (i = 1 to 8) 2-phase horizontal clocks 12 pre-scan elements Fast clear structure (FCA, VFCA)
VOS3
12
Uni- or Bi-directional Readout Register A
12
VOS4
GR BG 873 lines - Zone A 4 dummy lines (photosensitive)
GR BG
PAi (i = 1 to 4) vertical clocks
PBi (i = 1 to 4) vertical clocks 877 lines - Zone B 16 dark references (100% black) Full-field Image Sensor 3500 x 2300 active pixels
16 dark references (100% black)
8 insulating columns (photosensitive)
877 lines - Zone C PCi (i = 1 to 4) vertical clocks
4 dummy lines (photosensitive) 873 lines - Zone D First useful pixel on VOS1 output (Blue) GR BG GR BG
8 insulating columns (photosensitive)
PDi (i = 1 to 4) vertical clocks
VOS1
12
Uni- or Bi-directional Readout Register B
12
VOS2
LBi (i = 1 to 8) 2-phase horizontal clocks
Fast clear structure (FCB, VFCB)
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Architectural Overview
General Parameters
Table 2. General Parameters
Parameters Pixel size Number of useful pixels on one line Number of useful lines Number of readout register Number of outputs MPP technology Region of interest structures on readout registers Built-in antiblooming Pixel mode Readout register mode Note: 1. The design allows the full frame to be read through one, two or four outputs. Value 10 m x 10 m 2300 3500 2 4(1) yes yes no 4 phase 2 phase
Vertical Characteristics - AT71200M is made up of four zones, A, B, C and D. The configuration of each zone is shown in Table 3. Top to Bottom
Table 3. Vertical Characteristics
Zone A 873 active lines, 100% photosensitive B C D 4 dummy photosensitive lines 877 active lines, 100% photosensitive 877 active lines, 100% photosensitive 873 active lines, 100% photosensitive Configuration 4 dummy photosensitive lines
Horizontal Characteristics
Table 4 gives information on the characteristics seen by one output (VOS1, VOS2, VOS3 or VOS4) in different readout modes.
Table 4. Horizontal Characteristics
Readout Mode Characteristic Pre-scan elements Dark references Insulating elements Useful pixels One Output 12 16 8 2300 Two Outputs on Same Register 12 16 8 1150
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Color Mosaic Architecture
The color mosaic architecture corresponds to the Bayer standard represented by the following grid:
G B G B R G R G G B G B R G R G
Output Amplifiers
The charge packets are clocked to the output nodes and the charges are converted to voltages. The potential at the output node is read through two stage source follower amplifiers. Refer to Figure 3. Figure 3. On-chip Output Amplifier Structure
VDD
Output Node
VS
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Absolute Maximum Ratings*
Storage Temperature Range ......................... -55C to +150C Operating Temperature Range........................ -40C to +85C Thermal Cycling..........................................................15C/mn *NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability. Electrical limits of applied signals are given in Table 5. Shorting the video output to VSS or VDD, even temporarily, can permanently damage the output amplifier. Due to MPP mode or negative voltages, image zone gates and region of interest gates do not include ESD protection. To avoid degradation, the devices (including pins and package) should be handled with a grounded bracelet and stored on conductive layer used for shipment.
Table 5. Maximum Applied Voltages(1)
Signal Name LA[1:8] LB[1:8] S[1:4] VGL[1:4] VGS[1:4] VOS[1:4] VDD[1:4] VS[1:4] R[1:4] VDR[1:4] PA[1:4] PB[1:4] PC[1:4] PD[1:4] TA TB VDEA, VDEB VFCA, VFCB FCA FCB VSS Note: Parameter Readout A Register Clocks Readout B Register Clocks Summing Gate Readout Gate Output Gate Output Video Signal Amplifier Drain Supply Source Bias Reset Gate Reset Bias Image Zone A Clocks Image Zone B Clocks Image Zone C Clocks Image Zone D Clocks Transfer Gates Zone A Transfer Gates Zone B Shield Drains Region Of Interest Drains Region Of Interest Gates Zone A Region Of Interest Gates Zone B Substrate Bias 1. If not specified, all voltages are applied with respect to the substrate VSS. Min -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -15 and PA[other] - 20 -15 and PB[other] - 20 -15 and PC[other] - 20 -15 and PD[other] - 20 LA - 15 and PA[4] - 15 LB - 15 and PD[4 ] - 15 -0.3 -0.3 LA[1:8] - 15 LB[1:8] - 15 Max +15 +15 +15 +15 +15 +15 +15 +15 +15 +15 +15 and PA[other] + 20 +15 andPB[other] + 20 +15 and PC[1:4] + 20 +15 and PD[other] + 20 +15 and PA[4] + 15 +15 and PD[4] + 15 +15 +15 +15 +15 0 Unit V V V V V V V V V V V V V V V V V V V V V
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DC Characteristics
Symbol VS(1) VDD(1) VSS VGS VDR VGL VDE VFC Note: Parameter Source bias Amplifier drain supply Substrate bias Output gate Reset diode Readout gate Shield drain Regions of interest drains Minimum 0 14.5 0 7 13.5 3 3 12.5 Typical 0 15 0 7.5 14 3.5 5 13 8 14.5 4 6 13.5 Maximum 1 15.5 Unit V V V V V V V V Typical Currents < 12 mA < 12 mA - < 1 A < 5 A < 1 A < 1 A < 5 A
1. If corresponds to inactive output, may be stated to [3V, 7V] in order to reduce power consumption.
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Drive Clock Characteristics
Symbol Parameter State Low Pij(1)(2) Image Zone Clocks High Minimum -10 +2.5 Typical -9 +3 Maximum -8 +3.5 Unit V V Remarks For each A, B, C and D zone, the typical capacitances to drive are CPij approx. 12 nF After the eight clocks have been grouped together to form the two clocks L1 and L2, the typical capacitances to drive for each register A or B are CL1 approx. 310 pF and CL2 approx. 310 pF For each Sj, the typical capacitance to drive is CSj approx. 40 pF For each Rj, the typical capacitance to drive is CRj approx. 40 pF For each Tm, the typical capacitance to drive is CTm approx. 150 pF For each FCm, the typical capacitance to drive is CFCm approx. 50 pF
Low
0
0
+0.5
V
Lmn(3)(4)
Readout Register Clocks
High
+7.5
+8
+9
V
Low Sj(2) Summing Gates High Low Rj(2) Reset Gates High Low Tm(3) Transfer Gates High FC inactive FCm(3) Region of Interest Gates Low High Notes: 1. 2. 3. 4. i = A, B, C or D j = 1, 2, 3 or 4 m = A or B n = 1, 2, 3, 4, 5, 6, 7 or 8
0 +7.5 +1 +8 -6 +2.5 -3.5 0 +3.5
0 +8 +2 +9 -5 +3 -2.5 0 +4
+0.5 +9 +3 +10 -4 +3.5 -2 +0.5 +4.5
V V V V V V V V V
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Operating Modes
Figure 4. Operating Modes
3508 transfers min NBV = 3508
1-2-3 modes
PA1=PB1=PC1=PD1= PA2=PB2=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB4=PC4=PD4=
TA = Low Level
For the required readout mode, the vertical and horizontal clocks must be tied together externally as shown in Figure 4.
VERTICAL TRANSFER 3508 transfers min 1754 transfers min NBV = 3508 NBV = 1754
4-5-6 modes 7-8-9 modes
A B C B PA1=PB1=PC1=PD1= PA2=PB2=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB4=PC4=PD4=
TA = A TB = A
2631 transfers min NBV = 2631
10-11-12 modes
PA1=PB1=PC1=PD1= PA2=PB2=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB4=PC4=PD4=
TA = A TB = A
A B C D
PA1=PB1=PC1=PD1= PA2=PB2=PC2=PD2= PA3=PB3=PC3=PD3= PA4=PB4=PC4=PD4=
TA = A
A B C D
A B C D
TB = A
TB = Low Level
3
Inactive
4
3
4
3
4
3
4
2336 PIXELS PERIODS NBH = 2336
4-7-10 modes 1-7-10 modes
LA1=LA3=LA5=LA8=L1 LA2=LA4=LA6=LA7=L2
Mode1
Mode4
Mode7
Mode10
HORIZONTAL TRANSFER
1 3 Inactive
2 4
1 3
Inactive
2 4
1 3
2 4
1 3
2 4
LB1=LB4=LB5=LB7=L1 LB2=LB3=LB6=LB8=L2
2336 PIXELS PERIODS NBH = 2336
LA1=LA4=LA5=LA7=L1 LA2=LA3=LA6=LA8=L2
Mode2
Mode5
Mode8
Mode11
5-8-11 modes 2-8-11 modes
1 3 Inactive
2 4
1 3
Inactive
2 4
1 3
2 4
1 3
2 4
LB1=LB3=LB5=LB8=L1 LB2=LB4=LB6=LB7=L2
1186 PIXELS PERIODS NBH = 1186
6-9-12 modes
LA1=LA4=LA5=LA8=L1 LA2=LA3=LA6=LA7=L2
Mode3
Mode6
Mode9
Mode12
1
2
1
Inactive
2
1
2
1
2
LB1=LB4=LB5=LB8=L1 LB2=LB3=LB6=LB7=L2
3-9-12 modes
Note:
Symbols A, B, C and D correspond to the clocks described in the full-frame mode timing diagrams. Abbreviations NBV and NBH correspond respectively to the vertical and horizontal number of transfers. The unused horizontal clocks (L, R, S) must be stated to higher level of L.
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Timing Diagrams
Figure 5. Full-frame Mode Timing Diagram
Cleaning Integration time Readout time
NBV pulses 1234 nbv
Cleaning
A ... B ... C ... D ...
... ... ... ...
NBH pulses
L1
See expanded view in Fig. 6
L2
R
Note:
A, B, C, D, L1 and L2 (command phases) and NBV and NBH (number of vertical transfers and number of horizontal transfers respectively) are defined in Figure 4.
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Figure 6. Line Timing Diagram
t0
A
B
C
D
t0 9 t0 t0
11 t0
L1 L2 R
First prescan
Figure 7. Region of Interest Operating Mode
Pij
First following line is a dummy line
Li1
Li2
FCi
ta
tb
ta
Fast clear startup
Note:
1 line clearance
Fast clear stop
Typical values of ta, tb, tc, ta 150 ns, tb 150 ns, tc 150 ns
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Table 6. Typical TR and TF (Time Rise, Time Fall) for Phases
Phase P1 P2 P3 P4 FC VFC L1 L2 S R Time 500 ns 500 ns 500 ns 500 ns 50 ns 50 ns 10 ns 10 ns 10 ns 4 ns
Frame Rate Characteristics
Table 7. Frame Rate Characteristics
One Output (Modes 1, 2, 3, 4) Without binning Note: Typical 2.8 fps Two Outputs (Modes 13, 14) Typical 5.1 fps Four Outputs (Mode 15) Typical 10.2 fps
* * *
Table 7 gives typical values for full-frame mode where: Horizontal pixel frequency = 25 MHz Vertical transfer time TV = 11 x t0 = 10 s (delay times before and after line transfer t1 = t2 = t0) Integration time = 0s:
Table 8. Electrical and Miscellaneous Characteristics
Symbol VREF ZOUT IDD(1) CVF TV FH Note: Parameters DC output level Output impedance Output amplifier supply current Charge-to-voltage conversion factor Vertical transfer time Maximum Readout pixel frequency 1. For each output. 7.3 5 25 Minimum Typical 10 230 10 7.6 10 - - 15 8.0 Maximum Unit V Ohms mA V/es MHz
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Electrooptical Data
Table 9. Performance Data(1)
Symbol VSAT R-Blue
(2)
Parameters Pixel saturation output voltage Responsivity blue Responsivity green Responsivity red Responsivity blue Responsivity green Responsivity red Photo response non uniformity, Image zone MPP mode Image zone non-MPP mode Readout register (non-MPP mode) Average dark signal Dark signal non-uniformity, Temporal RMS noise in darkness at BW = 150 MHz Dynamic range Linearity
Minimum 500 0.45 0.45 0.70
Typical 600 0.60 0.60 0.92 0.19 0.19 0.25 1 0.3 60 150 7 3.5 270 67 1 86
Maximum 700
Unit mV V/(J/cm2) V/(J/cm2) V/(J/cm2) V/(lux.s) V/(lux.s) V/(lux.s)
R-Green(2) R-Red(2) R-Blue(2) R-Green
(2)
R-Red(2) PRNU DSI1 DSI2 DSR VDS(3) DSNU VN DR
(3)
6
% VOS mV/s mV/s mV/s
20 5.5
mV mV V dB % % - -
MTF
(4) (5)
Modulated transfer function Vertical charge transfer efficiency (per stage) Horizontal charge transfer efficiency (per stage) 0.99995 0.99995
VCTE
0.999998 0.999998
HCTE(5) Notes:
1. General measurement conditions: TC = 25C (chip temperature) Vertical transfer time TV = 10 ms Readout pixel frequency FH = 5 MHz Readout through 4 outputs and standard mode 9 (see figure 4) 3200K Halogen lamp with 2 mm BG38 filter at f/11 aperture 2. Blue, Green, Red channels The responsivity are well balanced for 3800K source 3. Integration time Ti = 10s in darkness 4. Green 5. Output voltage > 10% VSAT
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Figure 8. Typical Spectral Response with BG38 Infrared Filter (2 mm thickness), light source powered between 400 and 700 nm
2.0 1.8 1.6 1.4 V/J/cm 1.2 1.0 0.8 0.6 0.4 0.2 0.0 350 400 450 500 550 nm 600 650 700 750
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Image Grade
Table 10. Image Grade(1)
Blemishes Grade E H Notes: Total 500 300
Table 10 gives results of image grade testing.
Cluster 1
(2)
Cluster 2
(2)
Column
(2)
D min 3 3
Total 30 10
D min 50 50
Total 6 0
D min 100
Total 4 0
D min(2) 150
1. Testing has been carried out under the following conditions: Operating temperature: 25C (unless otherwise specified) Illumination conditions: 3200K Halogen lamp with BG38 Infrared filter and f/11 aperture Integration time = 10s in darkness Test under illumination at 50% of saturation level Standard mode, TV = 10 s, FH = 5 MHz 2. D min: Minimum number of pixels separating defects in any direction. All occurences are non-contiguous.
Definitions
Defect Sizes
Type Blemish Cluster Description 1 x 1 defect Blemish grouping of not more than a given number of adjacent defects: 1 x 1 < cluster 1 size 2 x 2 2 x 2 < cluster 2 size 5 x 5 One-pixel-wide column with more than seven contiguous defective pixels
Column
Defects in Darkness
Type Blemish/Cluster Column Description Pixel signal deviation of more than 200 mV from the average output signal Column signal deviation of more than 20 mV from the average output signal
Defects under Illumination
Type Blemish/Cluster Column Description Pixel deviation of more than +20% or -30% from the average output signal Column deviation of more than 10% from the average output signal
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Package Drawing
2.0 0.1 0.46 0.05 38.0 0.38 19.5 0.1 6 1.20 +0.05 -0.30
33.02 0.40
Y = 42.80 0.075
38.0 0.1
19 18 17 16 15 14
50.60 0.51
8 X 2.54
6 first pixel 2.54 typ PNMLKJHGFEDCBA 5 2.54 typ
6 5 4 3 2 1
4.57 0.25
3 2
Z top = 1.73 +0.25 -0.41
3.26 0.33
X = 7.50 0.075
4.52 +0.4 -0.65
1 Anti-reflective window 400-700 nm 98% min transmission 2 Photosensitive area 3 Z top = optical distance between top surface and 2 4 Zbot = optical distance between back side and 2 5 pin A1 index mark 6 Mechanical references/die positionning (first pixel)
4 Zbot = 2.79 +0.22 -0.30 All dimensions in mm
45.72 0.5
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Ordering Information
Figure 9. Ordering Code Key
1 2 3 4 5 6 7 8 9 10 11
AT71200
Customer specification Technological variants Temperature range: C: 0 C to +70 C Quality assurance level
- : Standard screening
Package families: R: Pin Grid Array (PGA)
E = On chip color filter
Image grade: E: Standard H: High
Package variants: N: Non-sealed window R: Anti-reflective window
The following part numbers are available: * * AT71200MCRERE: version grade E AT71200MCRHRE: version grade H
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(c) Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper.
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